(1) Technical Field
This disclosure relates to electronic circuits, and more particularly to integrated circuit designs and methods using adaptive dynamic voltage scaling.
(2) Background
The translation of integrated circuit designs from circuit diagrams or hardware programming code to working integrated circuits (IC's) implemented in modern transistor technologies remains as much art as engineering. A significant challenge in fabricating IC's is to control circuit parameters (such as delay, transistor threshold voltage, and transistor transconductance parameters) in view of variations in the semiconductor fabrication process, IC supply voltage, and IC operating temperature (often abbreviated as “PVT”, for “Process”, “Voltage”, and “Temperature” parameters).
Process variations during IC manufacture can cause unpredictable and undesired variations of circuit parameters, which can adversely affect circuit performance. “Process variation” is the naturally occurring variation of the attributes of transistors (e.g., geometry, such as length and width, and film and oxide thickness, as well as doping concentrations, etc.) when integrated circuits are fabricated. In addition, the parameters of individual transistors vary from wafer-to-wafer (interprocess variation) and die-to-die (intraprocess variation). Process variation becomes particularly important as the dimensions of components of the IC became smaller (<65 nm) and the variation become a larger percentage of the full length or width of the devices. At some point, feature sizes approach fundamental dimensions, such as the size of atoms and the wavelength of usable light for patterning lithography masks.
The above circuit parameters generally exhibit complex relationships among each other. For example, threshold voltage and transconductance are important circuit parameters, yet very difficult to control in precision analog circuits. In particular, transistor threshold voltage is very critical in determining propagation speed for high speed, low voltage digital circuits.
In addition to the transistors themselves, there are other on-chip variation (OCV) effects that manifest themselves when devices within an IC get very small. These include PVT variation effects on on-chip interconnects as well as via structures. In addition, there are wafer-to-wafer and intra-wafer variations within the bulk material of wafers, both in initial form and post-doping.
In other words, circuit parameters tend to be process dependent. Thus, it is useful for a manufacturer to be able to compensate for process variations applicable to a particular IC design, taking into account a range of supply voltages and operating temperatures, in order to meet a design specification and maximize IC die yields for that design.
Another problem in the translation of IC design to IC die is that in modern advanced transistor technologies, the power supply voltage is much lower compared to older technologies. For example, in 180 nm fabrication technology the recommended power supply voltage is 1.8V, while for 130 nm fabrication technology the recommended voltage is 1.5V, and for 28 nm fabrication technology the recommended voltage is 1.0V (nominal). In order to enable fast transistors with low overdrive voltages and reduced power supply voltages, the threshold voltage of the transistors must be smaller to at least maintain or even increase the speed of the transistors. While decreasing the threshold voltage of the transistors in advanced technologies is mandatory to achieve the desired speed, it negatively impacts the current leakage performance of the technology: a smaller threshold voltage results in faster devices, but faster devices have higher current leakage.
A number of approaches have been taken to compensate for the problems engendered by PVT dependent characteristics of advanced IC's. For example, one approach to dealing with performance differences caused by unique die-to-die response to an applied power supply voltage (i.e., where the same power supply voltage is provided to nominally identical but differently performing IC dies) is to provide for dynamic voltage scaling on an IC. FIG. 1 is a block diagram of a typical dynamic voltage scaling circuit 100 in accordance with the prior art. Prior art dynamic voltage scaling (DVS) essentially includes the following:
Measurement of Local Voltage Dependent Die Characteristics:
Each IC is provided with means to measure the speed of the implementation technology as a function of applied voltage. Such means may be a voltage dependent test circuit 102, such as one or more ring oscillators based on standard cell digital gates (even for an analog IC). As is known in the art, the frequency (i.e., speed) of such ring oscillators is dependent on the process speed, applied voltage, operating temperature, and the implementation characteristics of the individual devices comprising each ring oscillator structure. The ring oscillators should be based on the standard cells sizes used in the design (e.g., 7-track, 10-track, 12-track, 14-track, etc.; a circuitry cell in a standard cell library is laid out relative to a grid defined by horizontal and vertical tracks, and a cell library is generally classified by its track height; for example, a 10-track library is composed of cells having heights of 10 tracks or an integer multiple thereof, and thus a 10-track library has smaller cell sizes than a 12-track library). Each ring oscillator also should be implemented using transistor types similar to the ones used on the IC in the region of the ring oscillator, such as ultra-high Vt (UHVT), high Vt (HVT), standard Vt (SVT), low Vt (LVT), and ultra-low Vt (ULVT) transistors.
Comparison of the Measured Value to a Target Value:
The output of the speed measuring means is compared to a target value determined in any of various known ways. For example, the output of a ring oscillator comprising the voltage dependent test circuit 102 may be compared against the output of a target frequency source 104 (which may be derived, for example, from a crystal oscillator and adjusted to a selected target value), using, for example, a comparator 106 comprising a delay-locked loop (DLL) to compare the target frequency and the measured frequency of each ring oscillator. The DLL output is a signal (generally a digital signal) that reflects the difference in frequency between the voltage dependent test circuit 102 and the target frequency source 104. Alternatively, a counter can be used to measure the periods of the ring oscillators to determine their speed.
Feedback Control of the Power Supply Voltage:
The output of the comparison of the target frequency and the measured frequencies from the comparator 106 is applied to a means for controlling an external power supply to the IC, such as a variable voltage regulator 108, which adjusts the applied power supply higher or lower depending on the result of the frequency comparison. For example, the output of the comparison may be a pulse width modulation (PWM) signal. The PWM duty cycle can be used in known fashion to increase or decrease the power supply voltage in order to match the speed of the ring oscillators to the target frequency. If the ring oscillators are operating too slow, the applied power supply voltage is increased; conversely, if the ring oscillators are operating too fast, the applied power supply voltage is decreased. A typical adjustment range for a power supply using this approach is about ±10% (e.g., for a normalized voltage value of 1.0, the range is from about 0.9 to 1.1). For example, for a 28 nm node process, the IC circuit supply voltage range (Vdd) may be limited to between 0.9 Vmin and 1.1 Vmax. In reality, many individual ICs could operate at voltages below the 0.9V limit (and thus dissipate less power), but because of the worst case units, the entire population must be subjected to this limit to secure sufficient margin with the prior art method.
An IC design normally would have multiple DVS cells 110 distributed judicially across the IC die such that the voltage dependent test circuits 102 (e.g., ring oscillators) rather thoroughly reflect the transistor speed variations that occur across the dimensions of the die. When using multiple DVS cells 110, some economies of scale will be readily apparent to those skilled in the art, such as having only one target frequency source 104 coupled to all DVS cells 110, and time sharing (multiplexing) a single comparator 106 with all DVS cells 110.
Despite such attempts to mitigate the effects of PVT dependent characteristics on the fabrication of advanced IC's, IC designers and manufacturers have still been conservative in their approach to setting margins for IC designs (i.e., acceptable ranges of circuit parameters that result in fully functional IC's that meet all design specifications despite PVT variations). While a conservative approach seemingly improves die yields, the result generally is larger dies and more power usage (and thus more heat), in order to achieve the required performance and speed. This is because of the relatively large safety margin necessary with the prior art method, where basically the worst case units dictate the treatment of the whole population, without an ability to adaptively optimize operating conditions for each individual case. For example, a designer may choose to use five sigma instead of four sigma (of the deviation values of the variance obtained in a characterization step) for setting the Vdd supply voltage margin to reduce the probability of failure from a few tens of parts per million (ppm) to a few ppm, making the design more reliable. But this conservative approach results in a higher operating Vdd, and thus higher power dissipation. Another example is when a designer chooses to use a ULVT device instead of an SVT device in critical circuits in order to obtain higher margin. However, doing so will result in a larger circuit size and higher leakage power.
Accordingly, there is a need for an IC design that compensates for the effects of PVT dependent characteristics on the fabrication of advanced IC's but results in lower margins, smaller die size, higher die yields, and lower power usage in comparison to the prior art. The disclosed method and apparatus addresses this need.